New methods and structures are constantly being introduced to increase the device density of integrated circuits. By this it is meant that the new methods and structures allow the individual components of an integrated circuit that is formed in a monolithic semiconducting substrate to be made smaller in size and placed closer together than they previously had been, thus placing a greater number of devices within a given surface area of the substrate than was previously possible. However, with the tremendous increase in device density comes new challenges, which were either less of an issue or not an issue at all at the prior lower device densities.
For example, as device densities increase, the number of electrically conductive traces used to electrically interconnect the individual devices also increases. Thus, more electrically conductive traces have to fit within the same amount of space as previously used, or in even a smaller amount of space, as the size of the integrated circuit is reduced. At first, the traces themselves could be made narrower, which provided more open space for the additional traces. When the traces could no longer be made narrower because of electrical conductance constraints, materials that were more electrically conductive were used, so that the traces could be made narrower still.
However, as device densities have continued to increase, even the narrower width of the more conductive materials tends to be insufficient, of itself, to allow for the continual increase in the number of electrically conductive traces that are required. One way to increase the conductivity of a trace without increasing the width, is to increase the thickness of the trace. However, current etching techniques, such as used to define the traces within a contiguously deposited layer of material, are typically not able to adequately define the thicker trace layers, because the aspect ratio of the etched areas between the traces becomes too great. In other words, the depth to which the area between adjacent traces must be etched is so deep, and the width of the etched area between adjacent traces is so narrow, that the methods used to define the traces tend to not adequately etch and define the traces.
Thus, in order to place the traces closer together, the electrically conductive layer needs to be relatively thinner. This is acceptable for some types of traces, such as signal traces. However other types of traces, such as power traces and ground traces, need to carry relatively higher current levels than signal traces. Therefore, forming power and ground traces at relatively thinner thicknesses so as to place the traces closer together tends to produce voltage drops that are unacceptable because of the increased resistance of the thinner traces.
There is a need, therefore, for a system of electrically interconnecting the devices within an integrated circuit, that will allow for even further increases in device densities.